Exemplary embodiments of the present invention relate to an input/output unit of a non-volatile memory device and a method for operating the same.
Memory devices are divided into a volatile memory device and a non-volatile memory device according to whether data are sustained when a power source is cut off. The volatile memory device loses data when a power source is cut off, and Dynamic Random Access Memory (DRAM) and Synchronous DRAM (SDRAM) belong to the category of volatile memory device. The non-volatile memory device sustains data although a power source is cut off, and flash memory device belongs to the category of non-volatile memory device.
FIG. 1 illustrates data inputted into input/output pads in a conventional non-volatile memory device.
Referring to FIG. 1, a write enable signal WE# toggles in a duration when data are inputted to input/output pads IO×8, and data are inputted in synchronization with a rising edge of the toggling write enable signal WE#.
In a conventional non-volatile memory device, one period tWC of the write enable signal WE# may be approximately 25 nm (which is approximately 40 MHz in frequency), and the non-volatile memory device generally includes 8 input/output pads IO×8. Therefore, the data may be inputted to the non-volatile memory device at a rate of approximately 40 MB/s.
Meanwhile, when the data are outputted from the non-volatile memory device through the input/output pads IO×8, the data are outputted in synchronization with a read enable signal RE#. The output of the data through the input/output pads IO×8 is performed basically the same as the input of the data therethrough except that the signal with which the data are synchronized is not the write enable signal WE# but the read enable signal RE#.
FIG. 2 illustrates a data input/write path in a conventional non-volatile memory device.
Referring to FIG. 2, a write path of the conventional non-volatile memory device includes a buffer 210, a latch 220, and first to third demultiplexers (DEMUX) 230, 240 and 250.
The data inputted into 8 input/output pads 200 are buffered by the buffer 210 operating in synchronization with the write enable signal WE#. Since the number of the input/output pads 200 is 8, the number of the output lines of the buffer 210 is 8, too.
The latch 220 latches the data obtained from the buffering in the buffer 210 in synchronization with the write enable signal WE#. The latch 220 has 8 output lines IDIN<0:7> as well.
The first demultiplexer 230 outputs the output of the latch 220 to the second demultiplexer 240 or the third demultiplexer 250 in response to a bank selection signal BANK_SEL. There are 16 lines GDL_B0<0:15> and GDL_B1<0:15> between the demultiplexer 230 and the demultiplexer 240 and between the demultiplexer 230 and the demultiplexer 250, respectively, and a low/high selection signal L/H_SEL determines to which line the output of the latch 220 is to be transferred among the 16 lines. The following Table shows where an output signal of the latch 220 is transferred based on the level of the low/high selection signal L/H_SEL and the bank selection signal BANK_SEL.
TABLE 1BANK_SELL/H_SELLine to receiveHHGDL_B1<8:15>HLGDL_B1<0:7>LHGDL_B0<8:15>LLGDL_B0<0:7>
The second demultiplexer 240 transfers the output of the first demultiplexer 230 on lines GDL_B0<0:15> to a bank 0 of a plane 0 and a bank 0 of a plane 1. Then, the data is stored in a bank 0 of an enabled plane between the plane 0 and the plane 1.
The third demultiplexer 250 transfers the output of the first demultiplexer 230 on lines GDL_B1<0:15> to a bank 1 of a plane 0 and a bank 1 of a plane 1. Then, the data is stored in a bank 1 of an enabled plane between the plane 0 and the plane 1.
FIG. 3 illustrates a data output/read path in the conventional non-volatile memory device.
Referring to FIG. 3, a read path of the conventional non-volatile memory device includes first and second multiplexers 310 and 320 and an output unit 330.
The first multiplexer 310 transfers data which are outputted form a core region and loaded on lines GDL_B0_P0<0:15>, GDL_B1_P0<0:15>, GDL_B1_P1<0:15>, and GDL_B0_P1<0:15> outputted to 32 lines GDL_B0<0:15> and GDL_B1<0:15> in response to a plane selection signal PLANE_SEL. When a plane 0 is selected based on the plane selection signal PLANE_SEL, the data on lines GDL_B0_P0<0:15> is transferred to the line GDL_B0<0:15>, and the data on lines GDL_B1_P0<0:15> is transferred to the line GDL_B1<0:15>. Also, when a plane 1 is selected based on the plane selection signal PLANE_SEL, the data on lines GDL_B0_P1<0:15> is transferred to the line GDL_B0<0:15>, and the data on lines GDL_B1_P1<0:15> is transferred to the line GDL_B1<0:15>.
The second multiplexer 320 selects a group of signals between the output signals of the first multiplexer 310 in response to a bank selection signal BANK_SEL and outputs the selected output signal to its output terminal IDOUT<0:7>. The output lines GDL_B0<0:15> and GDL_B1<0:15> of the first multiplexer 310 includes 16 lines, respectively. Which line of the signal is to be transferred to the output terminal IDOUT<0:7> of the second multiplexer 320 is determined based on the low/high selection signal L/H_SEL. The following Table 2 shows which lines are to be selected based on the level of the low/high selection signal L/H_SEL and the bank selection signal BANK_SEL.
TABLE 2BANK_SELL/H_SELLine to be selectedHHGDL_B1<8:15>HLGDL_B1<0:7>LHGDL_B0<8:15>LLGDL_B0<0:7>
The output unit 330 outputs the output data of the second multiplexer 320 to an input/output pad 340 in synchronization with the read enable signal RE#.
Although one bank includes 16 IOs in the non-volatile memory device, it may include 8 input/output pads. Therefore, to input/output data to/from one bank, the data is inputted/outputted over two cycles through the input/output pads. This method, however, consumes relatively significant time to input/output the data in the non-volatile memory device. If the number of the input/output pads is increased to 16, this concern may be addressed, but increasing the number of the input/output pads leads to an increase in the corresponding area inside a chip.